5

T6817

4670A–BCD–02/03

Table 2. Output Data Protocol

Note:

Bit 0 to 15 = high: overtemperature shutdown

Power-supply Fail

In case of over- or undervoltage at Pin VS, an internal timer is started. When the under-

voltage delay time (t

fail bit (PSF) in the output register is set and all outputs are disabled. When normal volt-

age is present again, the outputs are enabled immediately. The PSF bit remains high

until it is reset by the SRR bit in the input register.

Bit

Output (Status)

Register

Function

0TP

Temperature prewarning: high = warning (overtemperature shut-

down, see remark below)

1

Status LS1

Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load

(correct load condition is detected if the corresponding output is

switched off)

2

Status HS1

Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load

(correct load condition is detected if the corresponding output is

switched off)

3

Status LS2

Description, see LS1

4

Status HS2

Description, see HS1

5

Status LS3

Description, see LS1

6

Status HS3

Description, see HS1

7

n.u.

Not used

8

n.u.

Not used

9

n.u.

Not used

10

n.u.

Not used

11

n.u.

Not used

12

n.u.

Not used

13

SCD

Short circuit detected: set high, when at least one output is

switched off by a short circuit condition

14

INH

Inhibit: this bit is controlled by software (bit SI in input register)

and hardware inhibit (Pin 17). High = standby, low = normal

operation

15

PSF

Power supply fail: over- or undervoltage at Pin VS detected

After power-on reset, the input register has the following status:

Bit 15

(SI)

Bit 14

(SCT)

Bit 13

(OLD)

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

H

H

H

n.u.n.u.

n.u.n.u.n.u.n.u.

L

L

L

L

L

L

L