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ZL10038LDG Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL10038LDG Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 38 page  ZL10036 Data Sheet 10 Zarlink Semiconductor Inc. 24 P0 Out Switching port P0. ‘0’ = disabled (high impedance). ‘1’ = enabled. 25 LOCK Out Output which indicates that phase comparator phase and frequency lock has been obtained and that the varactor voltage is within ‘tune unlock’ window. This powers up in logic ‘0’ state. 26 VccRF +5 V voltage supply for RF 27 RFBYPASS Out RF Bypass differential outputs. AC couple outputs. Matching circuitry as per applications diagram (Figure 2). In applications where RF Bypass is not required, pins should not be connected. 28 RFBYPASS Out 29 VccRF +5 V voltage supply for RF 30 N/C Not connected. Ground externally. 31 RFIN In RF differential inputs. AC couple input. Matching circuitry as per applications diagram. 32 RFIN In 33 N/C Not connected. Ground externally. 34 RFAGC In RF analogue gain control input Pin Symbol Direction Function Schematics P0/P1 P0/P1 LOCK CMOS Digital Output LOCK CMOS Digital Output VccRF RFAGC 5k 20k Vref VccRF RFAGC 5k 20k Vref |
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