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N74F842D Datasheet(PDF) 2 Page - NXP Semiconductors |
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N74F842D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product data 74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 2 2004 Jan 23 FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • High impedance NPN base input structure minimizes bus loading • I IL is 20 µA for minimum bus loading • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • 48 mA sink current • Slim dual in-line 300 mil package • Broadside pinout DESCRIPTION The 74F841 and 74F842 bus interface latches are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the output is in the high-impedance state. The 74F842 is the inverted output version of the 74F841. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F841, 74F842 5.5 ns 60 mA ORDERING INFORMATION COMMERCIAL RANGE: VCC = 5 V ± 10%; Tamb = 0 °C to +70 °C Type number Package Name Description Version N74F841N, N74F842N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1 N74F841D, N74F842D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/0.033 20 µA / 20 µA LE Latch Enable input 1.0/0.033 20 µA / 20 µA OE Output Enable input (active-LOW) 1.0/0.033 20 µA / 20 µA Qn Data outputs 1200/80 24 mA / 48 mA Qn Data outputs 1200/80 24 mA / 48 mA NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state. |
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