Atmel ATWINC1500B-MU [DATASHEET]

Atmel-42487B-ATWINC1500B-MU_Datasheet_03/2016

3

3

T a b l e o f C o n t e n t s

1

Ordering Information and IC Marking ........................................................................ 5

2

Block Diagram ............................................................................................................. 5

3

Pinout and Package Information ................................................................................ 6

3.1

Pin Description ......................................................................................................................................6

3.2

Package Description .............................................................................................................................8

4

Electrical Specifications ............................................................................................. 9

4.1

Absolute Ratings ...................................................................................................................................9

4.2

Recommended Operating Conditions ...................................................................................................9

4.3

DC Electrical Characteristics ............................................................................................................... 10

5

Clocking 10

5.1

Crystal Oscillator ................................................................................................................................. 10

5.2

Low Power Oscillator........................................................................................................................... 11

6

CPU and Memory Subsystems ................................................................................. 12

6.1

Processor ............................................................................................................................................ 12

6.2

Memory Subsystem............................................................................................................................. 12

6.3

Non-volatile Memory (eFuse) .............................................................................................................. 12

7

WLAN Subsystem...................................................................................................... 13

7.1

MAC

13

7.1.1

Features ................................................................................................................................. 13

7.1.2

Description.............................................................................................................................. 13

7.2

PHY

14

7.2.1

Features ................................................................................................................................. 14

7.2.2

Description.............................................................................................................................. 14

7.3

Radio

14

7.3.1

Receiver Performance ............................................................................................................ 14

7.3.2

Transmitter Performance ........................................................................................................ 16

8

External Interfaces .................................................................................................... 17

8.1

I2C Slave Interface .............................................................................................................................. 17

8.2

I2C Master Interface ............................................................................................................................ 19

8.3

SPI Slave Interface.............................................................................................................................. 19

8.4

UART

22

8.5

Wi-Fi/Bluetooth Coexistence ............................................................................................................... 23

8.6

GPIOs

23

9

Power Management ................................................................................................... 24

9.1

Power Architecture .............................................................................................................................. 24

9.2

Power Consumption ............................................................................................................................ 25

9.2.1

Description of Device States................................................................................................... 25

9.2.2

Current Consumption in Various Device States...................................................................... 25

9.2.3

Restrictions for Power States ................................................................................................. 26

9.3

Power-Up/Down Sequence ................................................................................................................. 26

9.4

Digital I/O Pin Behavior during Power-Up Sequences......................................................................... 28