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GS882Z36B-100I Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers |
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GS882Z36B-100I Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 34 page Rev: 1.15 6/2001 5/34 © 1998, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Preliminary. GS882Z18/36B-11/100/80/66 BPR2000.002.14 Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins. Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock. U2 TMS I Scan Test Mode Select U3 TDI I Scan Test Data In U5 TDO O Scan Test Data Out U4 TCK I Scan Test Clock J2, C4, J4, R4, J6 VDD I Core power supply D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 VSS I I/O and Core Ground A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 VDDQ I Output driver power supply Function W BA BB BC BD Read H X X X X Write Byte “a” L L H H H Write Byte “b” L H L H H Write Byte “c” L H H L H Write Byte “d” L H H H L Write all Bytes L L L L L Write Abort/NOP L H H H H GS882Z18/36 BGA Pin Description Pin Location Symbol Type Description |
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