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M464S1724DTS-L7A Datasheet(PDF) 1 Page - Samsung semiconductor |
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M464S1724DTS-L7A Datasheet(HTML) 1 Page - Samsung semiconductor |
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1 / 11 page  M464S1724DTS Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM The Samsung M464S1724DTS is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724DTS consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S1724DTS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sock- ets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ± 0.3V power supply • MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,250mil) , double sided component Part No. Max Freq. (Speed) M464S1724DTS-L7C/C7C 133MHz (7.5ns @ CL=2) M464S1724DTS-L7A/C7A 133MHz (7.5ns @ CL=3) M464S1724DTS-L1H/C1H 100MHz (10ns @ CL=2) M464S1724DTS-L1L/C1L 100MHz (10ns @ CL=3) FEATURE GENERAL DESCRIPTION M464S1724DTS SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD PIN NAMES * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground SDA Serial data I/O SCL Serial clock DU Don ′t use NC No connection PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 DQ14 DQ15 VSS NC NC CLK0 VDD RAS WE CS0 CS1 DU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 DQ46 DQ47 VSS NC NC CKE0 VDD CAS CKE1 *A12 *A13 CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 DQ21 DQ22 DQ23 VDD A6 A8 V SS A9 A10/AP VDD DQM2 DQM3 V SS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 V SS **SDA VDD 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ53 DQ54 DQ55 VDD A7 BA0 V SS BA1 A11 VDD DQM6 DQM7 V SS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 V SS **SCL VDD * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Voltage Key |
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