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IDT72T3655L4BB Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72T3655L4BB Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 57 page  4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO 1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 DESCRIPTION: The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/ 72T36105/72T36115/72T36125 are exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits: • Flexible x36/x18/x9 Bus-Matching on both read and write ports • A user selectable MARK location for retransmit • User selectable I/O structure for HSTL or LVTTL • Asynchronous/Synchronous translation on the read or write ports • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 9 Mbit Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. TheinputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the input port is controlledbyaWriteClock(WCLK)inputandaWriteEnable( WEN)input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable ( REN)input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport the FIFO must be configured for Standard IDT mode, also the RCSshouldbe tiedLOWandthe OEinputusedtoprovidethree-statecontroloftheoutputs,Qn. The output port can be selected for either 2.5V LVTTL or HSTL operation, thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset. AnOutputEnable( OE)inputisprovidedforthree-statecontroloftheoutputs. AReadChipSelect( RCS)inputisalsoprovided,theRCSinputissynchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronousoperationoftheoutputport, RCSshouldbeenabled,heldLOW. Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required forhighspeeddatacommunication,toprovidetightersynchronizationbetween the data being transmitted from the Qn outputs and the data being received by theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith respect to EREN and ERCLK, this is very useful when data is being read at highspeed.TheERCLKand ERENoutputsarenon-functionalwhentheRead port is setup for Asynchronous mode. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating RENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A RENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Emptyflag)and PAF(ProgrammableAlmost-Fullflag). TheEFandFF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso provided, so that PAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WENtogetherwith LD oneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serial or parallel offset loading has been selected. During Master Reset ( MRS)thefollowingeventsoccur: thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmodeofthe PAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAFflags. If asynchronous PAE/PAF configuration is selected, thePAE is asserted LOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGHontheLOW- to-HIGH transition of WCLK. Similarly, the PAFisassertedLOWontheLOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Ifsynchronous PAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag Mode (PFM) pin. |
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