ZL30108

Data Sheet

5

Zarlink Semiconductor Inc.

1.0

Pin Description

Pin #

Name

Description

1GND

Ground. 0V

3LOCK

Lock Indicator (Output). This output goes to a logic high when the PLL is frequency

locked to the selected input reference.

4

REF_FAIL0

Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0

reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that

it is exhibiting abrupt phase or frequency changes.

5

REF_FAIL1

Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1

reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that

it is exhibiting abrupt phase or frequency changes.

8GND

Ground. 0V

9

MODE_SEL

Mode Select (Input). This input determines the mode of operation: See Table 3.

0: Normal mode (device locked to input reference)

1: Freerun mode

10

RST

Reset (Input). A logic low at this input resets the device. On power up, the RST pin must

be held low for a minimum of 300 ns after the power supply pins have reached the

minimum supply voltage. When the RST pin goes high, the device will transition into a

Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance.

11

OSCo

Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected

from this pin to OSCi. This output is not suitable for driving other devices. For clock

oscillator operation, this pin must be left unconnected.

12

OSCi

Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected

from this pin to OSCo. For clock oscillator operation, this pin must be connected to a

clock source.

13

IC

Internal Connection. Connect this pin to VDD.

14

15

16

GND

Ground. 0V

17

AGND

Analog Ground. 0V

18

19

20

F2ko

Multi Frame Pulse (Output). This is a CMOS 2 kHz active high 51 ns framing pulse,

which marks the beginning of a multi frame.

This clock output pad includes a Schmitt triggered input which serves as a PLL feedback

path; proper transmission-line termination should be applied to maintain reflections below

Schmitt trigger levels.