Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

IDT77105L25TFI Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT77105L25TFI
Description  PHY (TC-PMD) for 25.6 Mbps ATM Networks
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT77105L25TFI Datasheet(HTML) 8 Page - Integrated Device Technology

Back Button IDT77105L25TFI Datasheet HTML 4Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 5Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 6Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 7Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 8Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 9Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 10Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 11Page - Integrated Device Technology IDT77105L25TFI Datasheet HTML 12Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 24 page
background image
8 of 24
September 11, 2000
IDT77105
Upon reset or line re-connect, the IDT77105 receiver is typically not
symbol-synchronized. Synchronization is established when it receives a
command byte, usually the start-of-cell command preceding the first
received cell.
The IDT77105 monitors line conditions and can provide an interrupt if
the line is deemed 'bad'. The interrupt status register contains a Good
Signal Bit (address 0x01, bit 6 set to 0 = Bad signal initially) which shows
the status of the line per the following algorithm:
To declare “Good Signal” (from "Bad" to "Good"):
There is an up-down counter that counts from 7 to 0 and is initially
set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024
cycles = 204.8 symbols) and no "bad symbol" has been received, the
counter decreases by one (i.e., from 7 to 6). However, if at least one
"bad symbol" is detected during these 1,024 clocks, the counter is
increased by one with a maximum of 7 (i.e., from 6 back to 7). The Good
Signal Bit is set to 1 when this counter reaches 0. The Good Signal Bit
could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad
symbols have been received.
To declare 'Bad Signal' (from "Good" to "Bad"):
The same up-down counter counts from 0 to 7 (being at 0 to provide
a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the clock increases one (i.e., from 0 to 1). If it detects all "good symbols"
and no "bad symbols" in the next time period, the counter decreases one
(i.e., from 1 back to 0). The "Bad Signal" is declared when the counter
reaches 7. The Good Signal Bit could be set to 0 as quickly as 1,433
symbols (204.8 x 7) if at least one "bad symbol" is detected in each
204.8 symbols of seven consecutive groups of 204.8 symbols.
UTOPIA Interface
UTOPIA Interface
UTOPIA Interface
UTOPIA Interface
The 'UTOPIA' (Universal Test & Operations PHY Interface for ATM)
interface is used as the data path interface between the IDT77105 PHY
and other system elements such as the Segmentation and Reassembly
(SAR) device, or switching systems.
Overview
Overview
Overview
Overview
Cell data is transferred via separate Transmit and Receive synchro-
nizing clocks which are controlled by the SAR or other system compo-
nents. Transfer of data is synchronized at the cell level through the use
of a Start of Cell signal. This signal is asserted when the data transfer
path contains the first byte of a cell.
Since the PHY layer uses external clocks for data transfer synchroni-
zation, flow control signals are provided to allow both the external device
and the PHY to throttle the data transfer rate.
Receive data is transferred when the RxEnb signal is asserted by an
external device. The PHY also provides an RxEmpty signal to indicate
that no valid data is ready for transfer out of the PHY. This signal is
active if another read would cause a PHY buffer underflow. Along with
RxEmpty, RxClav (Receive Cell Available) indicates that a complete cell
has been received and is ready for transfer. Likewise, Transmit data is
also transferred using similar controls and handshake signals.
The Status and Control interface for the IDT77105 PHY is provided
to allow control of several functions such as Header Error Control (HEC)
processing, diagnostics, and error notification/management.
Figure 2
4
Octet
Interface
Control -
RECV
8
RxData
4
RxClk
RxEnb
RxEm pty
5
NRZI
Decoding
Rx +
Rx
4
4
PRNG
Scramble
Nibble
Next
Reset
RxSOC
RxR ef
32.0MHz
Clock
Synthesizer
&PLL
5b/4b
Decoding
Command
Byte
Detection,
Removal,
& Decode
De-
Scrambler
3445 drw 04
OSC
2 Cells


Similar Part No. - IDT77105L25TFI

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT77155 IDT-IDT77155 Datasheet
307Kb / 50P
   PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155L155 IDT-IDT77155L155 Datasheet
307Kb / 50P
   PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155L155PX IDT-IDT77155L155PX Datasheet
307Kb / 50P
   PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
More results

Similar Description - IDT77105L25TFI

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT77V1253 IDT-IDT77V1253 Datasheet
449Kb / 44P
   TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS
IDT77V106L25 IDT-IDT77V106L25 Datasheet
216Kb / 27P
   3.3V ATM PHY for 25.6 and 51.2 Mbps
IDT77155 IDT-IDT77155 Datasheet
307Kb / 50P
   PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77V1254L25 IDT-IDT77V1254L25 Datasheet
840Kb / 47P
   Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
logo
Bel Fuse Inc.
S558-5999-85 BEL-S558-5999-85 Datasheet
245Kb / 2P
   ATM 25.6 MBPS INTERFACEMODULE
logo
Integrated Device Techn...
IDT77V1264L200 IDT-IDT77V1264L200 Datasheet
390Kb / 49P
   Quad Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
IDT77V126L200 IDT-IDT77V126L200 Datasheet
229Kb / 30P
   Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
IDT77V107 IDT-IDT77V107 Datasheet
325Kb / 24P
   Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2
logo
Bel Fuse Inc.
S553-1084-04 BEL-S553-1084-04 Datasheet
259Kb / 2P
   ATM 25.6 MBPS INTERFACE MODULE
S556-2006-32 BEL-S556-2006-32 Datasheet
224Kb / 2P
   ATM 25.6 MBPS FILTER MODULE
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com