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ISP1181BBS Datasheet(PDF) 6 Page - NXP Semiconductors |
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ISP1181BBS Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 70 page Philips Semiconductors ISP1181B Full-speed USB peripheral controller Product data Rev. 02 — 07 December 2004 6 of 70 9397 750 13958 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. EOT 10 5 I End-Of-Transfer input (programmable polarity, see Table 21); used by the DMA controller to force the end of a DMA transfer to the ISP1181B DREQ 11 6 O DMA request output (4 mA; programmable polarity, see Table 21); signals to the DMA controller that the ISP1181B wants to start a DMA transfer DACK 12 7 I DMA acknowledge input (programmable polarity, see Table 21); used by the DMA controller to signal the start of a DMA transfer requested by the ISP1181B TEST1 13 8 I test input; this pin must be connected to VCC via an external 10 kΩ resistor TEST2 14 9 I test input; this pin must be connected to VCC via an external 10 kΩ resistor INT 15 10 O interrupt output; programmable polarity (active HIGH or LOW) and signalling (level or pulse); see Table 21 TEST3 16 11 O test output; this pin is used for test purposes only BUS_CONF0 17 12 I bus configuration selector; see Table 3 BUS_CONF1 18 13 I bus configuration selector; see Table 3 DATA15 19 14 I/O bit 15 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA14 20 15 I/O bit 14 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA13 21 16 I/O bit 13 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA12 22 17 I/O bit 12 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA11 23 18 I/O bit 11 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA10 24 19 I/O bit 10 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) GND 25 20 - ground supply Vref 26 21 - I/O pin reference voltage (3.3 V); no connection if VCC = 5.0 V DATA9 27 22 I/O bit 9 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA8 28 23 I/O bit 8 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA7 29 24 I/O bit 7 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) DATA6 30 25 I/O bit 6 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) Table 2: Pin description…continued Symbol[1] Pin Type Description TSSOP48 HVQFN48 |
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