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K4C89183AF Datasheet(PDF) 4 Page - Samsung semiconductor |
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K4C89183AF Datasheet(HTML) 4 Page - Samsung semiconductor |
4 / 55 page K4C89183AF - 4 - REV. 0.7 Jan. 2005 4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM DESCRIPTION K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera- tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper- ate fast core cycle compared with regular DDR SDRAM. K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition. FEATURES Parameter K4C89183AF F6 FB F5 tCK Clock Cycle Time (min) CL = 4 4.0 ns 4.5 ns 5.0 ns CL = 5 3.5 ns 3.75 ns 4.5 ns CL = 6 3.0ns 3.33 ns 4.0 ns tRC Random Read/Write Cycle Time (min) 20.0 ns 22.5 ns 25 ns tRAC Random Access Time (min) 20.0 ns 22.5 ns 25 ns IDD1S Operating Current (single bank) (max) 320mA 300mA 280mA IDD2P Power Down Current (max) 70mA 65mA 60mA • Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and CLK) inputs - CS, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. • Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum • Quad Independent Banks operation • Fast cycle and Short Latency • Uni-directional Data Strobe • Distributed Auto-Refresh cycle in 3.9us • Power Down Mode • Variable Write Length Control • Write Latency = CAS Latency-1 • Programable CAS Latency and Burst Length - CAS Laatency = 4, 5, 6 - Burst Length = 4 • Organization : 4,194,304 words x 4 banks x 18 bits • Power Supply Voltage VDD : 2.5V ± 0.125V • VDDQ : 1.4V ∼ 1.9V • 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL • Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch • Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD |
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