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IS61NP25618-133TQ Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS61NP25618-133TQ Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 20 page 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 11/30/00 IS61NP12832 IS61NP12836 IS61NP25618 IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI® SYNCHRONOUS TRUTH TABLE(1) Address Operation Used CS1 CS2 CS2 ADV WE BWx OE CKE CLK Not Selected Continue N/A X X X H X X X L ↑ Begin Burst Read External Address L H L L H X L L ↑ Continue Burst Read Next Address X X X H X X L L ↑ NOP/Dummy Read External Address L H L L H X H L ↑ Dummy Read Next Address X X X H X X H L ↑ Begin Burst Write External Address L H L L L L X L ↑ Continue Burst Write Next Address X X X H X L X L ↑ NOP/Write Abort N/A L H L L L H X L ↑ Write Abort Next Address X X X H X H X L ↑ Ignore Clock Current Address X X X X X X X H ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). BURST READ DESELECT BURST WRITE BEGIN READ BEGIN WRITE READ WRITE READ WRITE BURST BURST BURST DS DS DS READ DS DS READ WRITE WRITE BURST BURST WRITE READ STATE DIAGRAM |
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