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MT90871 Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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MT90871 Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 65 page  Data Sheet MT90871 5 Zarlink Semiconductor Inc. FP8i M10 Frame Pulse Input (5V Tolerant). This pin accepts the Frame Pulse signal. The pulse width may be active for 122ns or 244ns at the frame boundary and the Frame Pulse Width bit (FPW) of the Control Register must be set Low (default) for a 122ns and set High for a the 244ns pulse condition. The device will automatically detect whether an ST-BUS or GCI-BUS style frame pulse is applied. C8i P10 Master Clock Input (5V Tolerant). This pin accepts a 8.192MHz clock. The internal Frame Boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit of the Control Register. CS A10 Chip Select (5V Tolerant). Active low input used by the microprocessor to enable the microprocessor port access. This input is internally set LOW during a device RESET. DS C8 Data Strobe (5V Tolerant). This active low input is used in conjunction with CS to enable the microprocessor port read and write operations. R/W A9 Read/Write (5V Tolerant). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. A0 - A14 B1, B4, B5, D5, A3, A4, C6, B6, A5, A6, C7, B7, A7, A8, B8 Address 0 - 14 (5V Tolerant). These pins form the 15-bit address bus to the internal memories and registers. (Address A0 = LSB). D0 - D15 N7, P7, P6, N6, P5, M6, P4, N5, P3, P2, N3, N4, M5, N2, M4, M3 Data Bus 0 - 15 (5V Tolerant). These pins form the 16-bit data bus of the microprocessor port. (Data D0 = LSB). DTA D9 Data Transfer Acknowledgment (5V Tolerant). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH level. (Max. IOL = 10mA). TMS A11 Test Mode Select (5V Tolerant with internal pull-up). JTAG signal that controls the state transitions of the TAP controller. TCK B11 Test Clock (5V Tolerant). Provides the clock to the JTAG test logic. TDi B10 Test Serial Data In (5V Tolerant with internal pull-up). JTAG serial test instructions and data are shifted in on this pin. TDo A12 Test Serial Data Out (5V Tolerant Three-state Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. TRST A14 Test Reset (5V Tolerant with internal pull-up) Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low during power-up for JTAG testing. This pin must be held LOW for normal functional operation of the device. RESET C9 Device Reset (5V Tolerant with internal pull-up). This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0 - 15 and BSTo0 - 15 are set to a high or high impedance depending on the state of the LORS and BORS external control pins, respectively. It clears the device registers and internal counters. This pin must stay low for more than 2 cycles of input clock C8i for the reset to be invoked. Pin Description Table (continued) Name Package Coordinates Description |
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