DDR SDRAM

512MB Unbuffered SODIMM(based on sTSOP)

Rev. 1.3 March. 2004

Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Output Load Circuit (SSTL_2)

Output

Z0=50

Ω

Ω

Input/Output Capacitance

(VDD=2.5V, VDDQ=2.5V, TA= 25

°C, f=1MHz)

Parameter

Symbol

M470L6423EN0

Unit

Min

Max

Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )

CIN1

38

47

pF

Input capacitance(CKE0, CKE1)

CIN2

38

47

pF

Input capacitance(CS0, CS1)

CIN3

36

44

pF

Input capacitance( CLK0, CLK1,CLK2)

CIN4

36

40

pF

Input capacitance(DM0~DM7)

CIN5

12

14

pF

Data & DQS input/output capacitance(DQ0~DQ63)

Cout1

12

14

pF

Data input/output capacitance (CB0~CB7)

Cout2

12

14

pF

AC Operating Conditions

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

V

3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.31

V

3

Input Differential Voltage, CK and CK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2

AC Operating Conditions

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

V

3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.31

V

3

Input Differential Voltage, CK and CK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2