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PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 6 of 12
Switching Waveforms
Read Cycle No. 1[12, 13]
Read Cycle No. 2[13, 14]
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
Notes:
12. Device is continuously selected. OE = VIL CE1 = VIL or OE = VIL CE2 = VIH.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE1 transition LOW or CE2 transition to HIGH.
15. Data I/O is high impedance if OE = VIH.
16. If CE1 goes HIGH Or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE1
HIGH
VCC
SUPPLY
CURRENT
CE2
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE1
WE
OE
tHZOE
DATA IN VALID
NOTE 17
CE2
tSCE1
tSCE2