PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 4 of 26
Pin Definitions
Left Port
Right Port
Description
A0L–A17L
A0R–A17R
Address Inputs.
BE0L–BE7L
BE0R–BE7R
Byte Enable Inputs. Asserting these signals enables Read and Write opera-
tions to the corresponding bytes of the memory array.
BUSYL[2,5]
BUSYR[2,5]
Port Busy Output. When the collision is detected, a BUSY is asserted.
CL
CR
Input Clock Signal.
CE0L[9]
CE0R[9]
Active Low Chip Enable Input.
CE1L[8]
CE1R[8]
Active High Chip Enable Input.
DQ0L–DQ71L
DQ0R–DQ71R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to
enable the DQ data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications
between ports. The upper two memory locations can be used for message
passing. INTL is asserted LOW when the right port writes to the mailbox location
of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
LowSPDL[2,4]
LowSPDR[2,4]
Port Low Speed Select Input. When operating at less than 100 MHz, the
LowSPD disables the port DLL.
PORTSTD[1:0]L[2,4,5] PORTSTD[1:0]R[2,4,5] Port Address/Control/Data I/O Standard Select Input.
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read
from the dual port memory array.
READYL[2,5]
READYR[2,5]
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
CNT/MSKL[8]
CNT/MSKR[8]
Port Counter/Mask Select Input. Counter control input.
ADSL[9]
ADSR[9]
Port Counter Address Load Strobe Input. Counter control input.
CNTENL[9]
CNTENR[9]
Port Counter Enable Input. Counter control input.
CNTRSTL[8]
CNTRSTR[8]
Port Counter Reset Input. Counter control input.
CNTINTL[10]
CNTINTR[10]
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
WRPL[2,3]
WRPR[2,3]
Port Counter Wrap Input. After the burst counter reaches the maximum count,
if WRP is low, the unmasked counter bits will be set to 0. If high, the counter
will be loaded with the value stored in the mirror register.
RETL[2,3]
RETR[2,3]
Port Counter Retransmit Input. Counter control input.
FTSELL[2,3]
FTSELR[2,3]
Flow-Through Select. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
VREFL[2,5]
VREFR[2,5]
Port External High-Speed IO Reference Input.
VDDIOL
VDDIOR
Port IO Power Supply.
REV[2,4]L
REV[2,4]R
Reserved pins for future features.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both
ports. A master reset operation is required at power-up.
TRST[2,5]
JTAG Reset Input.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state
machine. State machine transitions occur on the rising edge of TCK.
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