PRELIMINARY
1M x 16 Static RAM
CY7C1061AV25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05331 Rev. **
Revised January 27, 2003
Features
• High speed
—tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 2.5 ± 0.2V
• 1.5V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
Functional Description
The CY7C1061AV25 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
Reading from the device is accomplished by enabling the chip
by taking CE1 LOW and CE2 HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH / CE2 LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1061AV25 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Selection Guide
-8
-10
-12
Unit
Maximum Access Time
810
12
ns
Maximum Operating Current
Commercial
300
275
260
mA
Industrial
300
275
260
Maximum CMOS Standby Current
Commercial/Industrial
50
50
50
mA
Logic Block Diagram
Pin Configuration
TSOP II (Top View)
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
43
42
16
15
29
30
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O15
A2
CE1
I/O2
I/O0
I/O1
BHE
A3
A4
18
17
20
19
I/O3 27
28
25
26
22
21
23
24
I/O6
I/O4
I/O5
I/O7
A16
A15
BLE
VCC
I/O14
I/O13
I/O12
I/O10
I/O9
I/O8
A14
A13
A12
A11
A9
A10
CE2
44
46
45
47
50
49
48
51
53
52
54
VSS
VCC
A19
A18
VCC
VCC
VSS
DNU (Do Not Use)
VSS
NC
VCC
I/O11
VSS
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
1M x 16
ARRAY
A0
4096 x 4096
I/O0–I/O7
OE
I/O8–I/O15
CE1
WE
BLE
BHE
A9
CE2
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