PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 7 of 26
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[17] An increment that results
in one or more of the unmasked bits of the counter being “0”
will de-assert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values,
but 1F0FF, 003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
x72 devices as a 144-bit single port SRAM in which the
counter of one port counts even addresses and the counter of
the other port counts odd addresses. This even-odd address
scheme stores one half of the 144-bit data in even memory
locations, and the other half in odd memory locations.
Notes:
16. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF.
The CYD18S72V has 18 address bits and a maximum address value of 3FFFF.
17. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
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