10

IDT7009L

High-Speed 128K x 8 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

2. To ensure that the earlier of the two ports wins.

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

7009L15

Com'l Only

7009L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY Access Time from Address Match

____

15

____

20

ns

BUSY Disable Time from Address Not Matched

____

15

____

20

ns

BUSY Acce ss Time from Chip Enable Low

____

15

____

20

ns

BUSY Acce ss Time from Chip Enable High

____

15

____

17

ns

5

____

5

____

ns

____

15

____

17

ns

Write Hold After

12

____

15

____

ns

0

____

0

____

ns

Write Hold After

12

____

15

____

ns

PORT-TO-PORT DELAY TIMING

Write Pulse to Data Delay

(1)

____

30

____

45

ns

Write Data Valid to Read Data Delay

(1)

____

25

____

30

ns

4839 tbl 14