256M GDDR SDRAM

K4D553235F-GC

- 8 -

Rev 1.6 (May 2005)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode Register

CAS Latency

Latency

000

Reserved

001

Reserved

010

Reserved

011

3

100

4

101

5

110

6

111

Reserved

Burst Length

Burst Type

Sequential

Interleave

0

0

0

Reserved

Reserved

00

1

2

2

01

0

4

4

01

1

8

8

1

0

0

Reserved

Reserved

1

0

1

Reserved

Reserved

1

1

0

Reserved

Reserved

1

1

1

Reserved

Reserved

Burst Type

Type

0

Sequential

1

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

MRS Cycle

Command

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum

0

CK, CK

Precharge

NOP

NOP

MRS

NOP

NOP

2

01

6

12

10

11

Any

NOP

All Banks

Command

RFU

0

RFU

DLL

TM

CAS Latency

BT

Burst Length

0MRS

1EMRS

DLL

DLL Reset

0No

1Yes

Test Mode

mode

0

Normal

1Test

NOP