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IDT72T18125L6-7BBI Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72T18125L6-7BBI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 55 page 11 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 2.5V ± 0.125V, TA = 0 °C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C) Symbol Parameter Min. Max. Unit ILI InputLeakageCurrent –10 10 µA ILO OutputLeakageCurrent –10 10 µA VOH(5) Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ-0.4 — V IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ-0.4 — V IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ-0.4 — V VOL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 ICC1(1,2) Active VCC Current (VCC = 2.5V) I/O = LVTTL — 40 mA I/O = HSTL — 60 mA I/O = eHSTL — 60 mA ICC2(1) Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA I/O = HSTL — 50 mA I/O = eHSTL — 50 mA IDT72T18105/72T18115/72T18125 ICC1(1,2) Active VCC Current (VCC = 2.5V) I/O = LVTTL — 50 mA I/O = HSTL — 70 mA I/O = eHSTL — 70 mA ICC2(1) Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA I/O = HSTL — 60 mA I/O = eHSTL — 60 mA NOTES: 1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH. 2. For the IDT72T18105/72T18115/72T18125, typical ICC1 calculation (with data outputs in Low-Impedance): for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz) for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz) For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical ICC1 calculation (with data outputs in Low-Impedance): for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz) for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz). 3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz) with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000 fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C, N= Number of outputs switching. 4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ). 5. Outputs are not 3.3V tolerant. |
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