SN65LVDS348, SN65LVDT348

SN65LVDS352, SN65LVDT352

SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003

7

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switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

2.5

4

6

ns

tPHL

Propagation delay time, high-to-low-level output

2.5

4

6

ns

td1

Delay time, failsafe disable time

9

ns

td2

Delay time, failsafe enable time

C10 F

0.3

1.5

µs

tsk(p)

Pulse skew (|tpHL1 – tpLH1|)

CL = 10 pF,

See Figure 3

200

ps

tsk(o)

Output skew‡

See Figure 3

150

ps

tsk(pp)

Part-to-part skew§

1

ns

tr

Output signal rise time

1.2

ns

tf

Output signal fall time

1

ns

tr

Output signal rise time

CL = 1 pF,

650

ps

tf

Output signal fall time

CL = 1 F,

See Figure 3

400

ps

tPHZ

Propagation delay time, high-level-to-high-impedance output

5

9

ns

tPLZ

Propagation delay time, low-level-to-high-impedance output

See Figure 4 and

5

9

ns

tPZH

Propagation delay time, high-impedance-to-high-level output

See Figure 4 and

Figure 5

8

12

ns

tPZL

Propagation delay time, high-impedance-to-low-level output

8

12

ns

† All typical values are at 25

°C and with a 3.3-V supply.

‡ tsk(o) is the magnitude of the time difference between the tPHL or tPLH of all receivers of a single device with all of their inputs connected together.

§ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

PARAMETER MEASUREMENT INFORMATION

VID

B or RIN–

VIB or VRIN–

VIA or VRIN+

VIC

(VIA + VIB)/2 or

(VRIN+ + VRIN–)/2

VOY or VROUT

IOY or IROUT

Y or ROUT

A or RIN+

IIA or IRIN+

IIB or IRIN–

Figure 1. Voltage and Current Definitions