SDRAM 128Mb F-die (x4, x8, x16)

CMOS SDRAM

Rev. 0.2 November. 2003

Preliminary

Parameter

Value

Unit

Input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

3.3V

1200

Ω

870

Ω

Output

50pF

Vtt = 1.4V

50

Ω

Output

50pF

Z0 = 50

Ω

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

Notes :

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

- 60 (x16 only)

- 75

Row active to row active delay

12

15

ns

1

RAS to CAS delay

18

20

ns

1

Row precharge time

18

20

ns

1

Row active time

42

45

ns

1

100

us

Row cycle time

60

65

ns

1

Last data in to row precharge

2

CLK

2

Last data in to Active delay

2 CLK + tRP

-

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

3

Number of valid output data

CAS latency=3

2

ea

4

CAS latency=2

-

1

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.