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SLG46108 Datasheet(PDF) 38 Page - Dialog Semiconductor |
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SLG46108 Datasheet(HTML) 38 Page - Dialog Semiconductor |
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38 / 70 page  000-0046108-108 Page 37 of 69 SLG46108 10.3 3-Bit LUT or Pipe Delay Macrocell There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CK) and Reset (nRST). The pipe delay cell is built from D Flip-Flop logic cells that provide the two user selectable output options (OUT0 and OUT1). The DFF cells are tied in series where the output of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT0 and OUT1 outputs to a 3-input mux that is controlled by reg <260:258> for OUT0 and reg <263:261> for OUT1. The 3-input MUX is used to control the selection of the amount of delay. The overall time of the delay is based on the clock used in the SLG46108 design. Each DFF cell has a time delay of the inverse of the clock time (either external clock or the RC Oscillator within the SLG46108). The sum of the number of DFF cells used will be the total time delay of the Pipe Delay logic cell. Figure 13. 3-bit LUT4 or Pipe Delay 3-bit LUT4 OUT IN1 IN0 reg <265:258> From Connection Matrix Output <23> From Connection Matrix Output <24> IN2 From Connection Matrix Output <25> 8 Flip-Flops IN nRST CK From Connection Matrix Output <24> From Connection Matrix Output <23> From Connection Matrix Output <25> reg <263:261> reg <260:258> To Connection Matrix Input <13> OUT1 OUT0 reg <392> 1 0 To Connection Matrix Input <12> reg <268> 0 1 |
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