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SLG46127 Datasheet(PDF) 57 Page - Dialog Semiconductor |
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SLG46127 Datasheet(HTML) 57 Page - Dialog Semiconductor |
57 / 88 page 000-0046127-101 Page 56 of 87 SLG46127 13.2 Programmable Delay Register Settings Table 41. Programmable Delay Register Settings Signal Function Register Bit Address Register Definition Programmable delay or filter output select reg <485> 0: programmable delay output 1: filter output Select the edge mode of programmable delay & edge detector reg <487:486> 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay Delay value select for programmable delay & edge detector (VDD = 3.3V, typical condition) reg <489:488> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns |
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