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SLG46127 Datasheet(PDF) 65 Page - Dialog Semiconductor |
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SLG46127 Datasheet(HTML) 65 Page - Dialog Semiconductor |
65 / 88 page 000-0046127-101 Page 64 of 87 SLG46127 17.3 Blocks Output States During POR Sequence To have a full picture of SLG46127 operation during powering and POR sequence, review the overview the macrocell output states during the POR sequence (Figure 45 describes the output signals states). First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high impedance state). Before the NVM is ready, all macrocell outputs are unpredictable (except the output PINs). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also output LOW. Only P DLY macrocell configured as edge detector becomes active at this time. After that input PINs are enabled. Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The last are output PINs that become active and determined by the input signals. Figure 45. Internal Block States during POR sequence Unpredictable Unpredictable Unpredictable Unpredictable Unpredictable Unpredictable Unpredictable Unpredictable VDD Input PIN_out to matrix LUT_out to matrix Programmable Delay_out to matrix Prog. Edge_Detector_out to matrix DFF/Latch_out to matrix Delay_out to matrix POR_out to matrix Ext. GPO VDD_out to matrix Determined by Input signals Determined by Input signals Starts to detect input edges Determined by Input signals Determined by Input signals Determined by Input signals Starts to detect input edges Determined by input signals Determined by External Signal Guaranteed HIGH before POR_GPI Determined by input signals OUT = IN without Delay Determined by initial state Determined by input signals OUT = IN without Delay Tri-state t t t t t t t t t t |
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