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SLG46127 Datasheet(PDF) 74 Page - Dialog Semiconductor |
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SLG46127 Datasheet(HTML) 74 Page - Dialog Semiconductor |
74 / 88 page 000-0046127-101 Page 73 of 87 SLG46127 LUT3_1 or DFF3/Latch reg <257:250> reg <250> DFF3 or Latch select 0: DFF function 1: Latch function reg <251> DFF3 output select 0: Q output 1: nQ output reg <252> DFF3 nRST/nSET select 0: nRST from matrix output 1: nSET from matrix output reg <253> DFF3 initial polarity select 0: Low 1: High reg <257:254> Unused if DFF/Latch selected Unused LUT3_2 data reg <265:258> LUT3_2 data LUT3_2 data LUT3_3 data reg <273:266> LUT3_3 data LUT3_3 data LUT3_4 or pipe number select reg <281:274> reg <276:274>: OUT0 select data (pipe number) reg <279:277>: OUT1 select data (pipe number) reg <281:280>: Unused if Pipe Delay selected Unused LUT3/DFF Select reg <282> LUT3_0 or DFF2 select 0: LUT3_0 1: DFF2 reg <283> LUT3_1 or DFF3 select 0: LUT3_1 1: DFF3 reg <284> LUT3_4 or Pipe Delay output select 0: LUT3_4 1: Pipe Delay LUT4_0 or Counter/Delay2 mode selection reg <300:285> reg <285> Counter/Delay2 mode selection 0: Delay Mode 1: Counter Mode reg <288:286> Counter/Delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter1 Overflow reg <296:289> Counter/Delay2 Control Data 1 – 255 (Delay time = (counter control data +2) /freq) reg <298:297> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for Delay & counter reset) 01: Delay on falling edge only (for Delay & counter reset Delay) 10: on rising edge only (for Delay & counter reset) 11: No Delay on either falling or rising edges / high level reset for counter mode reg <300:299> Unused is Counter/Delay2 selected Unused reg <301> LUT4_0 or Counter2 select 0: LUT4_0, 1: Counter2 0: LUT4_0 1: Counter2 reg <302> Force RC oscillator on 0: Auto Power on 1: Force Power on Register Bit Address Signal Function Register Bit Definition |
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