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SLG46127 Datasheet(PDF) 76 Page - Dialog Semiconductor

Part # SLG46127
Description  GreenPAK Programmable Mixed-signal Matrix
Download  88 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46127 Datasheet(HTML) 76 Page - Dialog Semiconductor

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Page 75 of 87
SLG46127
Counter/Delay 1
reg <341:328>
reg <328> Counter/Delay1 mode selection
0: Delay Mode
1: Counter Mode
reg <331:329> Counter/Delay1 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter0 Overflow
reg <339:332> Counter1 Control Data/Delay1 Time
Control
1-255: (Delay time = (counter control data +2) /freq)
reg <341:340> Delay1 Mode Select or asynchronous
counter reset
00: Delay on both falling and rising edges (for Delay
& counter reset)
01: Delay on falling edge only (for Delay & counter
reset)
10: Delay on rising edge only (for Delay & counter
reset)
11: No Delay on either falling or rising edges / high
level reset for counter mode
Counter/Delay 3
reg <355:342>
reg <342> Counter/Delay3 mode selection
0: Delay Mode
1: Counter Mode
reg <345:343> Counter/Delay3 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter2 Overflow
reg <353:346> Counter3 Control Data/Delay4 Time
Control
1-255: (Delay time = (counter control data +2) /freq)
reg <355:354> Delay3 Mode Select
00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No Delay on either falling or rising edges
Register Bit
Address
Signal Function
Register Bit Definition


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