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SLG46127 Datasheet(PDF) 1 Page - Dialog Semiconductor |
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SLG46127 Datasheet(HTML) 1 Page - Dialog Semiconductor |
1 / 88 page Silego Technology, Inc. Rev 1.01 000-0046127-101 Revised September 28, 2017 GreenPAK Programmable Mixed-signal Matrix with Dual 44 mΩ / 2 A P-FET SLG46127 Block Diagram General Description The SLG46127 GreenPAK combines the functionality and ver- satility of a GreenPAK Programmable Mixed-signal Matrix with the capabilities of Silego’s CuFET technology. Capable of in- tegrating a number common discrete ICs and passive compo- nents into a single device, the GreenPAK family’s SLG46127M enables high power switching with dual 2 A P-Ch MOSFETs. Features • Logic & Mixed Signal Circuits • Highly Versatile Macro Cells • Read Back Protection (Read Lock) • 1.8V (±5%) to 5V (±10%) Supply • Operating Temperature Range -40 °C to 85 °C • Dual 44 mΩ, 2 A P-Channel MOSFETs • Package • 1.6 x 2.0 x 0.55 mm MSTQFN 16L package • Pb-Free / Halogen-Free / RoHS compliant Applications • Power Sequencing with Complex Analog Control • Power Plane Component Size Reduction Project • LED Driver • Haptic Motor Driver • System RESET with Power Switch Pin Configuration VIN1 GPIO GPIO VIN0 GND 12 GPIO GPIO 1 16pin MSTQFN (Top View) VOUT1 67 14 13 VOUT0 VDD 2 3 4 5 11 10 9 8 15 16 PWR_SW_ON1 PWR_SW_ON0 15 16 3-bit LUT3_4 or Pipe Delay Programmable Delay RC Oscillator ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT3 CNT1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_3 3-bit LUT3_2 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_1 or DFF3 3bit LUT3_0 or DFF2 4-bit LUT4_0 or CNT2 FILTER_0 Additional Logic Functions Pin 1 GPIO Pin 2 GPIO Pin 3 GND Pin 4 VIN0 Pin 9 VIN1 Pin 8 VOUT1 Pin 11 GPIO Pin 10 GPIO P-FET Power Switch1 Vref P-FET Power Switch0 Pin 5 VOUT0 Pin 6 NC Pin 7 AGND Pin 12 VDD Pin 14 GPIO Pin 13 GPI Pin 16 PWR_SW _ON1 Pin 15 PWR_SW _ON0 |
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