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TMS320LF2407PZA Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320LF2407PZA Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 106 page  TMS320LF2407, TMS320LF2406, TMS320LF2402 TMS320LC2406, TMS320LC2404, TMS320LC2402 DSP CONTROLLERS SPRS094C – APRIL 1999 – REVISED OCTOBER 1999 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pin functions (continued) Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued) PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION EXTERNAL INTERRUPTS, CLOCK RS 133 93 93 28 Device reset. RS causes the ’240x to terminate execution and sets PC = 0. When RS is brought to a high level, execution begins at location zero of program memory. RS affects (or sets to zero) various registers and status bits. When the watchdog timer overflows, it initiates a system reset pulse that is reflected on the RS pin. ( ↑) PDPINTA 7 6 6 36 Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVA) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINTA is a falling-edge-sensitive interrupt. ( ↑) XINT1/ IOPA2 23 16 16 External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. ( ↑) XINT2/ADCSOC/ IOPD0 21 15 15 42 External user interrupt 2 and ADC start of conversion or GPIO. External “start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. ( ↑) CLKOUT/IOPE0 73 51 51 1 Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14) of the System Control and Status Register (SCSR). This pin can be used as a GPIO if not used as a clock output pin. ( ↑) PDPINTB 137 95 95 Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVB) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINT is a falling-edge-sensitive interrupt. ( ↑) OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS XTAL1/CLKIN 123 87 87 24 PLL oscillator input pin. Crystal input to PLL/clock source input to PLL. XTAL1/CLKIN is tied to one side of a reference crystal. XTAL2 124 88 88 25 Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference crystal. This pin goes in the high-impedance state when EMU1/OFF is active low. PLLF 11 9 9 38 Filter input 1 PLLVCCA 12 10 10 39 PLL supply (3.3 V) PLLF2 10 8 8 37 Filter input 2 BOOT EN /XF BOOT_EN 121 86 – 23 Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN) to update SCSR2.3 (BOOT_EN bit) during reset and then driven as an output signal for BOOT_EN / XF XF 121 86 86 23 bit) during reset and then driven as an output signal for XF. ROM devices do not have boot ROM, hence, no BOOT_EN modes. ( ↑) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO – General-purpose input/output pin. All GPIOs come up as input after reset. LEGEND: ↑ – Internal pullup ↓ – Internal pulldown |
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