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VSC8062 Datasheet(PDF) 8 Page - Vitesse Semiconductor Corporation |
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VSC8062 Datasheet(HTML) 8 Page - Vitesse Semiconductor Corporation |
8 / 20 page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Page 8 G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Coupling for Inputs Figure 7: AC-Coupling for DCLK, DCLKN Inputs DCLK, DCLKN Inputs Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple- ment inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differen- tially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the comple- mentary input. High-Speed Clock and Serial Data Inputs It is recommended that all high-speed clock and serial data inputs (CLK/CLKN for the VSC8061; DI/DIN and CLK/CLKN for the VSC8062) be AC-coupled. Figure 8 shows the configuration for a single-ended AC- coupling operation. In most situations, these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. The following is to assist in this application. All serial data and clock inputs have the same circuit topology, as shown in Figure 8. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the max- imum allowable amplitude. For single-ended, DC-coupling operations, it is recommended the user provide an external reference voltage which has better temperature and power supply noise rejection than the on-chip resis- tor divider. The external reference should have a nominal value as indicated in the table and can be connected to either side of the differential gate. VTT DCLK DCLKN VCC = GND VTT = -2V -1.32V -1.32V R| | = 1kΩ CIN CSE VTT Chip Boundary CIN typ = 0.1µF CSE typ = 0.1µF for single-ended applications ZO RT = ZO (Capacitor values are selected for DCLK = 155Mb/s.) |
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