VSP2262

11

SBMS011

TIMINGS

The CDS and the ADC are operated by SHP/SHD and their

derivative timing clocks generated by the on-chip timing

generator. The digital output data is synchronized with

ADCCK. See the VSP2262 “CDS Timing Specifications” for

the timing relationship among the CCD signal, SHP/SHD,

ADCCK and the output data. CLPOB is used to activate the

black level clamp loop during the OB pixel interval, and

CLPDM is used to activate the input clamping during the

dummy pixel interval. If the CLPDM pulse is not available in

your system, the CLPOB pulse can be used in place of

CLPDM as long as the clamping takes place during black

pixels (refer to the “Input Clamp and Dummy Pixel Clamp”

section for more detail). The clock polarities of SHP/SHD,

CLPOB and CLPDM can be independently set through the

serial interface (refer to the “Serial Interface” section for more

detail). The descriptions and the timing diagrams in this data

sheet are all based on the polarity of Active LOW (default

value). In order to keep a stable and accurate OB clamp level,

we recommend CLPOB should not be activated during PBLK

active period. Refer to the “Preblanking and Data Latency”

section for more detail. In Stand-by mode, ADCCK, SHP,

SHD, CLPOB and CLPDM are internally masked and pulled

HIGH.

POWER SUPPLY, GROUNDING AND DEVICE

DECOUPLING RECOMMENDATIONS

The VSP2262 incorporates analog circuitry and a very

high-precision, high-speed ADC that are vulnerable to any

extraneous noise from the rails or elsewhere. For this reason,

it should be treated as an analog component and all supply

analog supply of the system. This will ensure the most

consistent results, since digital power lines often carry high

levels of wideband noise that would otherwise be coupled

into the device and degrade the achievable performance.

Proper grounding, short lead length, and the use of ground

planes are also very important for high-frequency designs.

Multi-layer PC boards are recommended for the best perfor-

mance, since they offer distinct advantages like minimizing

ground impedance, separation of signal layers by ground

layers, etc. It is highly recommended that analog and digital

ground pins of the VSP2262 be joined together at the IC and

be connected only to the analog ground of the system. The

driver stage of the digital outputs (B[11:0]) is supplied

separated from the other supply pins completely, or at least

with a ferrite bead.

It is also recommended to keep the capacitive loading on the

output data lines as low as possible (typically less than

15pF). Larger capacitive loads demand higher charging

current surges that can feed back into the analog portion of

the VSP2262 and affect the performance. If possible, exter-

nal buffers or latches should be used, providing the added

benefit of isolating the VSP2262 from any digital noise

activities on the data lines. In addition, resistors in series

with each data line may help minimize the surge current.

Values in the range of 100

Ω to 200Ω will limit the instan-

taneous current the output stage has to provide for recharg-

ing the parasitic capacitances as the output levels change

from LOW to HIGH, or HIGH to LOW. Due to high

operation speed, the converter also generates high-frequency

current transients and noises that are fed back into the supply

and reference lines. This requires the supply and reference

pins to be sufficiently bypassed. In most cases, 0.1

µF ce-

ramic chip capacitors are adequate to decouple the reference

pins. Supply pins should be decoupled to the ground plane

with a parallel combination of tantalum (1

µF to 22µF) and

ceramic (0.1

µF) capacitors. The effectiveness of the decou-

pling largely depends on the proximity to the individual pin.

Special attention must be paid to the bypassing of COB,

BYPP2 and BYPM, since these capacitor values determine

important analog performances of the device.