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XRT75R03D Datasheet(PDF) 4 Page - Exar Corporation |
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XRT75R03D Datasheet(HTML) 4 Page - Exar Corporation |
4 / 134 page XRT75R03D REV. 1.0.2 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER I TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................. 1 FEATURES .................................................................................................................................................... 1 APPLICATIONS .............................................................................................................................................. 1 TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2 RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2 Figure 1. Block Diagram of the XRT 75R03D ................................................................................................... 2 Figure 2. Pin Out of the XRT75R03D ............................................................................................................... 3 ORDERING INFORMATION ................................................................................................................... 3 TABLE OF CONTENTS .................................................................................................................................... I PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS ...................................................................... 4 TRANSMIT LINE SIDE PINS ............................................................................................................................ 8 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS .................................................................... 10 RECEIVE LINE SIDE PINS ............................................................................................................................ 17 GENERAL CONTROL PINS ........................................................................................................................... 18 CONTROL AND ALARM INTERFACE ............................................................................................................... 20 JITTER ATTENUATOR INTERFACE ................................................................................................................. 20 POWER SUPPLY AND GROUND PINS ............................................................................................................ 23 XRT75R03D PIN LISTING IN NUMERICAL ORDER ........................................................................................ 25 1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 30 1.1 NETWORK ARCHITECTURE ................................................................................................................................ 30 Figure 3. Network Redundancy Architecture ................................................................................................. 30 1.2 POWER FAILURE PROTECTION .......................................................................................................................... 30 1.3 SOFTWARE VS HARDWARE AUTOMATIC PROTECTION SWITCHING ...................................................................... 30 2.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 31 TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 31 TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................... 31 3.0 TIMING CHARACTERISTICS ............................................................................................................ 32 Figure 4. Typical interface between terminal equipment and the XRT75R03D (dual-rail data) ...................... 32 Figure 5. Transmitter Terminal Input Timing ................................................................................................... 32 Figure 6. Receiver Data output and code violation timing .............................................................................. 33 Figure 7. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 33 4.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 34 4.1 E3 LINE SIDE PARAMETERS: ............................................................................................................................. 34 Figure 8. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... 34 TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ........................... 35 Figure 9. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ 36 TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 36 TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . 37 Figure 10. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 37 TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 38 TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ..... 38 Figure 11. Microprocessor Serial Interface Structure ...................................................................................... 39 Figure 12. Timing Diagram for the Microprocessor Serial Interface ................................................................ 39 TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ..... 39 FUNCTIONAL DESCRIPTION: ........................................................................................ 41 5.0 The Transmitter Section: ................................................................................................................. 41 Figure 13. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 41 Figure 14. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 41 5.1 TRANSMIT CLOCK: ........................................................................................................................................... 42 5.2 B3ZS/HDB3 ENCODER: .................................................................................................................................. 42 5.2.1 B3ZS Encoding: ................................................................................................................................. 42 5.2.2 HDB3 Encoding: ................................................................................................................................. 42 |
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