XR88C92CP datasheet(6/32 Pages) EXAR

Part #	XR88C92CP

Description	DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

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Manufacturer	EXAR [Exar Corporation]

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XR88C92/192

6

Rev. 1.31

SYMBOL DESCRIPTION (* 44 pin TQFP)

IP3

3

2

41

I

Multi-purpose input or Channel A transmit external clock port

input. The transmit data is clocked on the falling edge of the

clock.

IP4

43

39

37

I

Multi-purpose input or Channel A receive external clock input.

The transmit data is clocked on the rising edge of the clock.

IP5

42

38

36

I

Multi-purpose input or Channel B Transmit external clock

input. The transmit data is clocked on the falling edge of the

clock.

IP6

41

37

35

I

Multi-purpose input or Channel B receive external clock input.

The transmit data is clocked on the rising edge of the clock.

-CS

39

35

33

I

Chip select (active low). A low at this pin enables the serial

port / CPU data transfer operation.

D0-D7

28,18

25,16

22,12

Bi-directional data bus. Eight bit, three state data bus to

27,19

24,17

21,13

I/O

transfer information to or from the CPU. D0 is the least

26,20

23,18

20,14

significant bit of the data bus and the first serial data bit to be

25,21

22,19

19,15

received or transmitted.

-IOW

9

8

3

I

Write strobe (active low). A low on this pin will transfer the

contents of the CPU data bus to the addressed register.

-IOR

10

9

4

I

Read strobe (active low). A low on this pin will transfer the

contents of the XR88C92/192 register to CPU data bus.

VCC

44

40

38,39

Pwr

Power supply input, 2.97V to 5.5V.

N.C.

1,12

11,23

No Connection.

23,34

Symbol

Signal

Pin Description

44

40

44*

type

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