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XR68C92IJ Datasheet(PDF) 7 Page - Exar Corporation |
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XR68C92IJ Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 32 page  XR68C92/192 7 Rev. P1.10 INTERNAL CONTROL LOGIC The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic allows ac- cess to the registers within the XR68C92/192 and performs various commands by decoding the four reg- ister-select lines (A1 through A4). Besides the four register-select lines, there are three other inputs to the internal control logic from the R/-W (Read/write), which allows read and write transfers between the CPU and XR68C92/192 via the data bus buffer, -CS (chip-select), which is the XR68C92/192 chip-select, and -RESET (reset), which initializes or resets. The -DTACK (data transfer acknowledge) signal, which is asserted during read, write, or interrupt-acknowledge cycles, is the internal control logic output. The -DTACK signal indi- cates to the CPU that data has been latched on a CPU write cycle or that valid data is present on the data bus during a CPU read cycle or -IACK (interrupt-acknowl- edge) cycle. TIMING LOGIC The timing logic consists of a crystal oscillator, a baud- rate generator (BRG), a programmable 16-bit counter/timer (C/T), and four clock selectors. The crystal oscillator operates directly from a 3.6864 MHz crystal connected across the XTAL1 and XTAL2 in- puts or from an external clock of the appropriate frequency connected to XTAL1. The XTAL1 clock serves as the basic timing reference for the baud-rate generator, the C/T, and other internal circuits. The baud-rate generator operates from the XTAL1 clock input and can generate 28 commonly used data communication baud rates ranging from 50 to 230.4k by producing internal clock outputs at 16 times the actual baud rate. The C/T can produce a 16X clock for other baud rates by counting down its programmed clock source. Other baud rates can also be derived by connecting 16X or 1X clocks to certain input port pins that have alternate functions as receiver or transmitter clock inputs. Four clock selectors allow the indepen- dent selection of any of these baud rates for each receiver and transmitter. Users can program the 16 bit C/T within the XR68C92/192 to use one of several clock sources as its input. The output of the C/T is available to the internal clock selectors and can also be pro- grammed to appear at parallel output OP3. In the timer mode, the C/T acts as a programmable divider and can generate a square-wave output at OP3. In the counter mode, the C/T can be started and stopped under program control. When stopped, the CPU can read its contents. The counter counts down the number of pulses stored in the concatenation of the C/T upper register and C/T lower register and produces an inter- rupt. This is a system-oriented feature that can be used to record timeouts when implementing various applica- tion protocols. INTERRUPT CONTROL LOGIC The following registers are associated with the interrupt control logic: • Interrupt Mask Register (IMR) • Interrupt Status Register (ISR) • Auxiliary Control Register (ACR) • Interrupt Vector Register (IVR) A single active-low interrupt output (-INT) can notify the processor that any of eight internal events has occurred. These eight events are described in the discussion of the interrupt status register (ISR). User can program the interrupt mask register (IMR) to allow only certain conditions to cause -INT to be asserted while the CPU can read the ISR to determine all currently active interrupting conditions. When an ac- tive-low interrupt acknowledge signal (-IACK) from the processor is asserted while the XR68C92/192 has an interrupt pending, the XR68C92/192 will place the contents of the interrupt vector register (IVR) on the data bus and assert the data transfer acknowledge signal (-DTACK). If the XR68C92/192 has no pending interrupt, it ignores -IACK cycles. In addition, users can program the interrupt outputs from the transmitters, the receivers, and the C/T to appear at the parallel output pins OP3 through OP7. DATA BUS BUFFER The data bus buffer provides the interface between the external and internal data buses. It is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling CPU and XR68C92/192 via the eight parallel data lines (D0 through D7). |
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