9

MT933

General

The following is the register set that is implemented in the MT933 device:

The interface to these registers is via the MDC and MDIO signals. The address of the MT933 is specified by

the PA<4:0> static inputs The MD command is issued by the controller and can be read or write:

command

preamble

start data

op code

phy address

reg number

TA

Data

READ

32 bits of 1

01

10

5 bits

5 bits

Z0

16 bit from phy

WRITE

32 bits of 1

01

01

5 bits

5 bits

10

16 bit from MAC

SC = Self clear

RO = read only

RW = read or write

LL = latch low until register read

LH = latch high until register read

Register Set

reg 0 - control register

Bit

Bit name

Description

Default

R/W

0.15

Reset

1 = PHY reset

0

RW

0 = Normal operation

SC

0.14

Loopback

1 = Loopback mode active

0

RW

0 = Normal operation

0.13

Speed

1 = 100 Mbps

1

RW

selection

0 = 10 Mbps

0.12

ANEG

1 = Enable ANEG process

1

RW

enable

0 = Disable ANEG process

0.11

Power down

1 = Power down active

0

RW

0 = Normal operation

0.10

Isolation

1 = isolation in process

0

RW

0 = Normal operation

0.9

Restart

1 = Restart the ANEG process

0

RW

ANEG

0 = Normal operation

SC

0.8

Duplex

1= Full Duplex mode

1

RW

selection

0 = Half duplex mode

0.7

Collision

1 = Collision test active

0

RW

test

0 = Normal operation

0.6:0

Reserved

Write as 0 ignore on read.