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MT90823AL1 Datasheet(PDF) 6 Page - Zarlink Semiconductor Inc |
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MT90823AL1 Datasheet(HTML) 6 Page - Zarlink Semiconductor Inc |
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6 / 46 page  MT90823 Data Sheet 6 Zarlink Semiconductor Inc. 35 8 5 N3 TDO Test Serial Data Out (3.3 V Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. 36 9 6 M4 TCK Test Clock (5 V Tolerant Input): Provides the clock to the JTAG test logic. 37 10 7 N4 TRST Test Reset (3.3 V Input with internal pull-up): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up, or held low, to ensure that the MT90823 is in the normal functional mode. 38 11 8 M5 IC Internal Connection (3.3 V Input with internal pull- down): Connect to VSS for normal operation. This pin must be low for the MT90823 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements. 39 12 9 N5 RESET Device Reset (5 V Tolerant Input): This input (active LOW) puts the MT90823 in its reset state to clear the device internal counters, registers and bring STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100 nsec to reset the device. 40 13 10 M6 WFPS Wide Frame Pulse Select (5 V Tolerant Input): When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. 41 - 48 14-21 11 - 18 N6,M7,N7,N8, M8,N9,M9,N10 A0 - A7 Address 0 - 7 (5 V Tolerant Input): When non- multiplexed CPU bus operation is selected, these lines provide the A0 - A7 address lines to the internal memories. 49 22 19 N11 DS/RD Data Strobe / Read (5 V Tolerant Input): For Motorola multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8- D15) as outputs. Pin Description (continued) Pin # Name Description 84 PLCC 100 MQFP 100 LQFP 120 BGA |
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