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PC755CMGSU350LE Datasheet(PDF) 4 Page - ATMEL Corporation

Part # PC755CMGSU350LE
Description  PowerPC 755/745 RISC Microprocessor
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PC755CMGSU350LE Datasheet(HTML) 4 Page - ATMEL Corporation

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PC755/745
2138D–HIREL–06/03
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
Floating-point Unit and a 32-entry FPR File
Support for IEEE-754 standard single and double precision floating point
arithmetic
Hardware support for divide
Hardware support for denormalized numbers
Single-entry reservation station
Supports non-IEEE mode for time-critical operations
System Unit
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
Load/Store Unit
One cycle load or store cache access (byte, half-word, word, double-word)
Effective address generation
Hits under misses (one outstanding miss)
Single-cycle unaligned access within double word boundary
Alignment, zero padding, sign extend for integer register file
Floating point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Cache and TLB instructions
Big and Little-endian byte addressing supported
Misaligned Little-endian supported
Level 1 Cache structure
32K, 32 bytes line, 8-way set associative instruction cache (iL1)
32K, 32 bytes line, 8-way set associative data cache (dL1)
Cache locking for both instruction and data caches, selectable by group of
ways
Single-cycle cache access
Pseudo least-recently used (PLRU) replacement
Copy-back or Write Through data cache (on a page per page basis)
Supports all PowerPC memory coherency modes
Non-Blocking instruction and data cache (one outstanding miss under hits)
No snooping of instruction cache
Level 2 (L2) Cache Interface (not implemented on PC745)
Internal L2 cache controller and tags; external data SRAMs
256K, 512K, and 1-Mbyte 2-way set associative L2 cache support
Copyback or write-through data cache (on a page basis, or for all L2)
Instruction-only mode and data-only mode.
64 bytes (256K/512K) or 128 bytes (1M) sectored line size


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