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SC16C550BIB48 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SC16C550BIB48 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 47 page Philips Semiconductors SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Product data Rev. 02 — 14 December 2004 7 of 47 9397 750 14446 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. CS0, CS1, CS2 14, 15, 16 9, 10, 11 12, 13, 14 I Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these three inputs select the UART. When any of these inputs are inactive, the UART remains inactive (refer to AS description). CTS 40 38 36 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. This pin has no effect on the UART’s transmit or receive operation. D7-D0 9-2 4-2, 47-43 8-1 I/O Data bus. Eight data lines with 3-State outputs provide a bi-directional path for data, control and status information between the UART and the CPU. DCD 42 40 38 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DCD) of the modem status register indicates that DCD has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD changes levels, an interrupt is generated. DDIS 26 22 23 O Driver disable. DDIS is active (LOW) when the CPU is not reading data. When active, DDIS can disable an external transceiver. DSR 41 39 37 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. DTR 37 33 33 O Data terminal ready. When active (LOW), DTR informs a modem or data set that the UART is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a Master Reset, during loop mode operation, or clearing the DTR bit. INT 33 30 30 O Interrupt. When active (HIGH), INT informs the CPU that the UART has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register or an enabled modem status interrupt. INT is reset (deactivated) either when the interrupt is serviced or as a result of a Master Reset. NC 1, 12, 23, 34 1, 6, 13, 21, 25, 36, 37, 48 - - Not connected. OUT1, OUT2 38, 35 34, 31 34, 31 O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level as a result of Master Reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. RCLK 10 5 9 I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the UART. Table 2: Pin description…continued Symbol Pin Type Description PLCC44 LQFP48 DIP40 |
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