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AT49LH00B4-33TC Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT49LH00B4-33TC Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 36 page  10 AT49LH00B4 3379B–FLASH–9/03 FWH Write Cycle FWH write cycles are used to send commands to the device and to program data into the memory array. Valid FWH write cycles begin with a START field of 1110b being sent to the device. Following the IDSEL, MADDR, and MSIZE fields, the master sends one byte of data to the FWH device during the next two clock cycles. The data is sent one nibble at a time with the low nibble being output first followed by the high nibble. After the data has been sent, the master will send a 2-clock TAR field to the FWH device to indicate that it is turning control of the LPC bus back over to the FWH. After the second clock of the TAR phase, the FWH device assumes control of the bus and drives a “ready” SYNC field to verify that it has received the data. The FWH device will then send a 2-clock TAR field to the master to indicate that it is turning control of the bus back over to the master. Figure 3. FWH Write Cycle Note: 1. Field contents are valid on the rising edge of the present clock cycle. CLK FWH4/LFRAME FWH/LAD[3:0] 1110b IDSEL A15-A12 A27-A24 A23-A20 A19-A16 A11-A8 A7-A4 A3-A0 0000b High-Z 0000b D3-D0 D7-D4 1111b High-Z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 11 START IDSEL MADDR MSIZE TAR1 RSYNC DATA DATA TAR0 TAR1 TAR0 Table 5. FWH Write Cycle Clock Cycle Field Name Field Value (1) FWH/LAD[3:0] FWH/LAD[3:0] Direction Comments 1 START 1110b IN FWH4/LFRAME must be active (low) for the device to respond. Only the last START field (before FWH4/LFRAME transitioning high) should be recognized. The START field contents indicate a FWH memory write cycle. 2 IDSEL 0000b to 1111b IN Indicates which FWH memory device should respond. If the IDSEL field matches the strapping values on ID[3:0], then that particular device will respond to subsequent commands. 3 - 9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred with the most significant nibble first. 10 MSIZE 0000b (indicates 1 byte) IN The MSIZE field indicates how many bytes will be transferred. The device only supports single-byte operations, so MSIZE must be 0000b. 11 DATA YYYY IN YYYY is the least significant nibble of the data byte. The data byte is either any valid Flash command or the data to be programmed into the memory array. 12 DATA YYYY IN YYYY is the most significant nibble of the data byte. 13 TAR0 1111b IN then float In this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus “turn-around cycle”. 14 TAR1 1111b (float) Float then OUT The device takes control of the bus during this clock cycle. 15 RSYNC 0000b (ready) OUT During this clock cycle, the device will generate a “ready” SYNC indicating that the data byte has been received. 16 TAR0 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a turn- around cycle. 17 TAR1 1111b (float) Float then IN The FWH memory device floats its outputs, and the master regains control of the bus during this clock cycle. |
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