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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-3033/3



MAY 2003

3.3 VOLT CMOS ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9,

2,048 x 9, 4,096 x 9,

8,192 x 9, 16,384 x 9

IDT72V01, IDT72V02

IDT72V03, IDT72V04

IDT72V05, IDT72V06

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEATURES:

7205/7206 family

— Active: 180 mW (max.)

— Power-down: 18 mW (max.)

°°°°°C to +85°°°°°C) is available

FUNCTIONAL BLOCK DIAGRAM

W

WRITE

CONTROL

READ

CONTROL

R

FLAG

LOGIC

EXPANSION

LOGIC

XI

WRITE

POINTER

RAM

ARRAY

512 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9

16,384 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA OUTPUTS

EF

FF

XO/HF

RS

FL/RT

3033 drw 01

DESCRIPTION:

The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO

memoriesthatoperateatapowersupplyvoltage(Vcc)between3.0Vand3.6V.

Their architecture, functional operation and pin assignments are identical to

those of the IDT7201/7202/7203/7204/7205/7206. These devices load and

emptydataonafirst-in/first-outbasis.TheyuseFullandEmptyflagstoprevent

data overflow and underflow and expansion logic to allow for unlimited

expansion capability in both word size and depth.

The reads and writes are internally sequential through the use of ring

pointers, with no address information required to load and unload data. Data

is toggled in and out of the devices through the use of the Write (

W) and Read

(

R) pins. The devices have a maximum data access time as fast as 25 ns.

The devices utilize a 9-bit wide data array to allow for control and parity bits

at the user’s option. This feature is especially useful in data communications

applications where it is necessary to use a parity bit for transmission/reception

error checking. They also feature a Retransmit (

RT) capability that allows for

reset of the read pointer to its initial position when

RTispulsedLOWtoallowfor

retransmission from the beginning of data. A Half-Full Flag is available in the

single device mode and width expansion modes.

These FIFOs are fabricated using IDT’s high-speed CMOS technology. It

has been designed for those applications requiring asynchronous and simul-

taneous read/writes in multiprocessing and rate buffer applications.