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IDT70V24S35JI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V24S35JI Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 22 page 1 ©2000 Integrated Device Technology, Inc. MARCH 2000 DSC-2911/8 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL UBL BUSY L A11L A0L 2911 drw 01 LBL CEL OEL I/O8L-I/O15L I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/ S R/ WR UBR BUSYR LBR CER OER I/O8R-I/O15R I/O0R-I/O7R A11R A0R R/ WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 12 12 IDT70V24S/L HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM Features x x x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x x x x x High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) x x x x x Low-power operation – IDT70V24S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V24L Active: 380mW (typ.) Standby: 660 µW (typ.) x x x x x Separate upper-byte and lower-byte control for multiplexed bus compatibility x x x x x IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device x x x x x M/ S = VIH for BUSY output flag on Master M/ S = VIL for BUSY input on Slave x x x x x BUSY and Interrupt Flag x x x x x On-chip port arbitration logic x x x x x Full on-chip hardware support of semaphore signaling between ports x x x x x Fully asynchronous operation from either port x x x x x LVTTL-compatible, single 3.3V (±0.3V) power supply x x x x x Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP x x x x x Industrial temperature range (-40°C to +85°C) is available for selected speeds Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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