16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

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11

LATCH

XOR/

DECODE

LATCH

LVDS

RECEIVER

LATCH

LATCH

DAC

OUTIP

OUTIN

LATCH

XOR/

DECODE

LATCH

LATCH

DAC

OUTQP

OUTQN

FSADJ

TORB

SELIQN

XORP

XORN

CLKN

CLKP

CLK

INTERFACE

DATA15–

DATA0

+1.2V

REFERENCE

POWER-DOWN

BLOCK

REFIO

DACREF

PD

GND

SELIQP

MAX5878

Figure 1. MAX5878 High-Performance, 16-Bit, Dual Current-Steering DAC

Detailed Description

Architecture

The MAX5878 high-performance, 16-bit, dual current-

steering DAC (Figure 1) operates with DAC update rates

up to 250Msps. The converter consists of input registers

and a demultiplexer for single-port operation, followed by

a current-steering array. During operation, the input data

registers demultiplex the single-port data bus. The cur-

rent-steering array generates differential full-scale cur-

rents in the 2mA to 20mA range. An internal

current-switching network, in combination with external

50

Ω termination resistors, converts the differential output

currents into dual differential output voltages with a 0.1V

to 1V peak-to-peak output voltage range. An integrated

+1.2V bandgap reference, control amplifier, and user-

selectable external resistor determine the data convert-

er’s full-scale output range.

Reference Architecture and Operation

The MAX5878 supports operation with the internal

+1.2V bandgap reference or an external reference volt-

age source. REFIO serves as the input for an external,

low-impedance reference source. REFIO also serves as

a reference output when the DAC operates in internal

reference mode. For stable operation with the internal

reference, decouple REFIO to GND with a 1µF capaci-

tor. Due to its limited output drive capability, buffer

REFIO with an external amplifier when driving large

external loads.