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XE3005 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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XE3005 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 32 page Data Sheet XE3005/XE3006 7 D0212-116 2.1.4 Digital Loop Back In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level tests. The digital loop back mode can be selected through register J. 2.1.5 Operating Frequency A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency (MCLK/div_factor) should not exceed 12.288 MHz. The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is ‘1’. 2.1.6 Serial Audio Interface The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the bit serial clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC corresponds to the rate at which the Audio Serial Interface will put out succeeding frames. One frame always corresponds to one sample. One frame always contains 2 channels. Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed ratio as defined by the following relation: FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor). The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin SDI) or out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can select to use the first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or out the data samples. The table below shows some examples of the relationships between MCLK, BCLK and FSYNC MCLK Div_factor BCLK FSYNC 2048 kHz 1 256 kHz 8 kHz 8192 kHz 4 256 kHz 8 kHz 5120 kHz 1 640 kHz 20 kHz 22579.2 kHz 2 1411.2 kHz 44.1 kHz The table below shows the possible functional configurations of the serial audio interface CODEC supported protocol master LFS (long frame sync) slave LFS (long frame sync), SFS (short frame sync) By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the signals BLCK, FSYNC and supply to the CODEC. In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only. The register J is used for the different setups of the serial audio interface. |
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