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SN74AUP1G04DRLR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP1G04DRLR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 12 page SN74AUP1G04 LOW POWER SINGLE INVERTER GATE SCES571A − JUNE 2004 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUP1G04YEPR _ _ _HC_ −40 °C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUP1G04YZPR _ _ _HC_ −40 °C to 85°C SOT (SOT-23) − DBV Tape and reel SN74AUP1G04DBVR H04_ SOT (SC-70) − DCK Tape and reel SN74AUP1G04DCKR HC_ SOT (SOT-533) − DRL Reel of 4000 SN74AUP1G04DRLR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT A OUTPUT Y H L L H logic diagram (positive logic) AY 24 |
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