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VSC7182TW Datasheet(PDF) 1 Page - Vitesse Semiconductor Corporation |
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VSC7182TW Datasheet(HTML) 1 Page - Vitesse Semiconductor Corporation |
1 / 18 page VITESSE SEMICONDUCTOR CORPORATION ® Advance Product Information VSC7182 Quad Transceiver for Gigabit Ethernet and Fibre Channel G52307-0, Rev 2.2 Page 1 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Features General Description The VSC7182 is a full-speed quad Fibre Channel and Gigabit Ethernet transceiver IC. Each of the four transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters and serializes the data onto high-speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7182 contains on-chip Phase-Lock Loop (PLL) circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams. The VSC7182 also includes a receiver squelch circuit to control the parallel data bus in the absence of serial input. VSC7182 Block Diagram (1 of 4 Channels) • Four Complete Transmitter/ Receiver Functions in a Single Integrated Circuit • Full Fibre Channel (T11) and Gigabit Ethernet (IEEE 802.3z) Compliance • 1.05Gb/s to 1.36Gb/s Operation per Channel • Common or Per-Channel Transmit Byte Clocks • TTL or PECL Reference Clock Input • Receiver Squelch Circuit • Common and Per-Channel, Serial and Parallel Loopback Controls • Common Comma Detect Enable Inputs • Per-Channel Comma Detect Outputs • Cable Equalization in Receivers • Replacement For Agilent’s HDMP-1682 • 3.3V Power Supply, 2.67 W Max Dissipation • 208-Pin, 23mm BGA Packaging RFCT CAP0 CAP1 RFC+ RFC- RFCM SI+ SI- Q D Serial to Parallel Clock Recovery ÷10 Comma RXi[0:9] Clock Parallel to Serial SO+ SO- 10 10 Q D Q D Detect D Q D Q Multiply Unit x10/x20 1 0 RCi1 RCi0 SYNi SYNC PLUP SLPN TXi[0:9] TCi 4 4 1 0 Loopback Control LPNi 4 RCM ÷10/ ÷20 SEL RFCO0 RFCO1 LTCN |
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