3

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

WED9LC6416V

January 20001

OUTPUT FUNCTIONAL DESCRIPTIONS

Symbol

Type

Signal

Polarity

Function

SSCLK

Input

Pulse

Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.

SSADS

When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation

SSOE

Input

Pulse

Active Low

to be executed by the SSRAM.

SSWE

SSCE

Input

Pulse

Active Low

SSCE disable or enable SSRAM device operation.

SDCLK

Input

Pulse

Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

SDCE

Input

Pulse

Active Low

SDRAS

When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation

SDCAS

Input

Pulse

Active Low

to be executed by the SDRAM.

SDWE

Address bus for SSRAM and SDRAM

rising clock edge.

Input

Level

—

Input

Level

—

Data Input/Output are multiplexed on the same pins.

Output

Input

Pulse

Vcc, Vss

Supply

Power and ground for the input buffers and the core logic.

Supply

Data base power supply pins, 3.3V (2.5V future).