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AM29DL322GT90 Datasheet(PDF) 5 Page - Advanced Micro Devices

Part No. AM29DL322GT90
Description  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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 5 page
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February 9, 2005
Am29DL32xG
3
DA TA SH EET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .........................................................10
Word/Byte Configuration .................................................................................10
Requirements for Reading Array Data ......................................................... 10
Writing Commands/Command Sequences .................................................. 11
Accelerated Program Operation ................................................................ 11
Autoselect Functions ...................................................................................... 11
Simultaneous Read/Write Operations
with Zero Latency ............................................................................................... 11
Standby Mode .........................................................................................................11
Automatic Sleep Mode ....................................................................................... 11
RESET#: Hardware Reset Pin ......................................................................... 12
Output Disable Mode ........................................................................................ 12
Table 2. Device Bank Divisions ..........................................................12
Table 3. Top Boot Sector Addresses .................................................13
Table 4. Top Boot SecSiTM Sector Addresses ......................................14
Table 5. Bottom Boot Sector Addresses .............................................15
Table 6. Bottom Boot SecSiTM Sector Addresses ................................16
Autoselect Mode ..................................................................................................17
Table 7. Autoselect Codes, (High Voltage Method) .............................17
Sector/Sector Block Protection and Unprotection ...................................18
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...............................................................18
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...............................................................18
Write Protect (WP#) ........................................................................................ 19
Temporary Sector Unprotect ......................................................................... 19
Figure 1. Temporary Sector Unprotect Operation ............................... 19
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms......................................................... 20
SecSiTM (Secured Silicon) Sector
Flash Memory Region ........................................................................................ 21
Factory Locked: SecSi Sector Programmed and Protected At the Fac-
tory ...................................................................................................................... 21
Customer Lockable: SecSi Sector NOT Programmed or Protected At
the Factory ........................................................................................................ 21
Hardware Data Protection .............................................................................. 21
Low VCC Write Inhibit ............................................................................... 22
Write Pulse “Glitch” Protection ............................................................... 22
Logical Inhibit .................................................................................................. 22
Power-Up Write Inhibit ............................................................................... 22
Common Flash Memory Interface (CFI) . . . . . . .22
Table 10. CFI Query Identification String............................................. 22
Table 11. System Interface String...................................................... 23
Table 12. Device Geometry Definition................................................. 23
Table 13. Primary Vendor-Specific Extended Query............................. 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . .24
Reading Array Data ........................................................................................... 24
Reset Command ..................................................................................................25
Autoselect Command Sequence ....................................................................25
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence ..........................................................................................25
Byte/Word Program Command Sequence .................................................25
Unlock Bypass Command Sequence ........................................................26
Figure 3. Program Operation............................................................. 26
Chip Erase Command Sequence ...................................................................26
Sector Erase Command Sequence ................................................................ 27
Erase Suspend/Erase Resume Commands .................................................. 27
Figure 4. Erase Operation.................................................................. 28
Table 14. Command Definitions......................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ............................................................................................30
Figure 5. Data# Polling Algorithm...................................................... 30
RY/BY#: Ready/Busy# .........................................................................................31
DQ6: Toggle Bit I ................................................................................................ 31
Figure 6. Toggle Bit Algorithm........................................................... 31
DQ2: Toggle Bit II .............................................................................................. 32
Reading Toggle Bits DQ6/DQ2 ..................................................................... 32
DQ5: Exceeded Timing Limits ........................................................................ 32
DQ3: Sector Erase Timer ................................................................................ 32
Table 15. Write Operation Status .......................................................33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform............................ 34
Figure 8. Maximum Positive Overshoot Waveform.............................. 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)................................................................ 36
Figure 10. Typical ICC1 vs. Frequency................................................. 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup....................................................................... 37
Figure 12. Input Waveforms and Measurement Levels........................ 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Read Operation Timings.................................................... 38
Figure 14. Reset Timings................................................................... 39
Word/Byte Configuration (BYTE#) ..............................................................40
Figure 15. BYTE# Timings for Read Operations................................... 40
Figure 16. BYTE# Timings for Write Operations.................................. 40
Erase and Program Operations .......................................................................41
Figure 17. Program Operation Timings............................................... 42
Figure 18. Accelerated Program Timing Diagram................................ 42
Figure 19. Chip/Sector Erase Operation Timings................................. 43
Figure 20. Back-to-back Read/Write Cycle Timings............................. 44
Figure 21. Data# Polling Timings (During Embedded Algorithms)........ 44
Figure 22. Toggle Bit Timings (During Embedded Algorithms)............. 45
Figure 23. DQ2 vs. DQ6.................................................................... 45
Temporary Sector Unprotect ........................................................................46
Figure 24. Temporary Sector Unprotect Timing Diagram..................... 46
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram. 47
Alternate CE# Controlled Erase and Program Operations .................48
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................................ 49
Erase And Programming Performance . . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
TSOP Pin and Fine-Pitch BGA Capacitance. . . . 50
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 51
FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm .......... 51
FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ..................................... 52
TS 048—Thin Small Outline Package .......................................................... 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 55




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