X4283/85 – Preliminary Information

Characteristics subject to change without notice.

2 of 22

REV 1.17 11/27/00

www.xicor.com

standard Vtrip thresholds are available, however, Xicor’s

unique circuits allow the threshold to be reprogrammed

to meet custom requirements or to fine-tune the thresh-

old for applications requiring higher precision.

The memory portion of the device is a CMOS Serial

EEPROM array with Xicor’s Block Lock protection. The

array is internally organized as 64 bytes per page. The

device features an 2-wire interface and software proto-

col allowing operation on an 2-wire bus.

PIN CONFIGURATION

SDA

SCL

3

2

4

1

6

7

5

8

WP

RST/RST

SCL

RST/RST

3

2

4

1

6

7

5

8

WP

SDA

8-Pin JEDEC SOIC

8-Pin TSSOP

PIN DESCRIPTION

Pin

(SOIC)

Pin

(TSSOP)

Name

Function

13

Device Select Input

24

Device Select Input

3

5

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

RESET goes active if the Watchdog Timer is enabled and SDA remains either

HIGH or LOW longer than the selectable Watchdog time out period. A falling edge

on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes

active on power up and remains active for 250ms after the power supply stabilizes.

46

Ground

5

7

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain

or open collector outputs. This pin requires a pull up resistor and the input buffer

is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

6

8

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

71

WP

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to

the control register.

82

Supply Voltage