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PHK13N03LT Datasheet(PDF) 2 Page - NXP Semiconductors |
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PHK13N03LT Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors PHK13N03LT TrenchMOS™ logic level FET Product data Rev. 01 — 23 June 2003 2 of 12 9397 750 11611 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ T j ≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ T j ≤ 150 °C; RGS =20kΩ -30 V VGS gate-source voltage (DC) - ±20 V ID drain current (DC) Tsp =25 °C; VGS =10V; Figure 2 and 3 - 13.8 A Tsp = 100 °C; VGS =10V; Figure 2 - 8.7 A IDM peak drain current Tsp =25 °C; pulsed; tp ≤ 10 µs; Figure 3 -55 A Ptot total power dissipation Tsp =25 °C; Figure 1 - 6.25 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp =25 °C - 5.7 A ISM peak source (diode forward) current Tsp =25 °C; pulsed; tp ≤ 10 µs - 55 A |
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